Compute through power loss hardware approach for processing device having nonvolatile logic memory

ABSTRACT

A computing device apparatus facilitates use of a deep low power mode that includes powering off the device&#39;s CPU by including a hardware implemented process to trigger storage of data from the device&#39;s volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

RELATED APPLICATION(S)

This application is a continuation of and claims priority to U.S. patent application Ser. No. 16/451,260 filed Jun. 25, 2019, which is a continuation of U.S. patent application Ser. No. 15/016,449 filed on Feb. 5, 2016, now U.S. Pat. No. 10,331,203 granted Jun. 25, 2019, which claims the priority to U.S. Provisional Patent Application No. 62/272,473, filed Dec. 29, 2015, each of which are incorporated herein by reference in its entirety.

TECHNICAL FIELD

This invention generally relates to processing devices having nonvolatile memory and, in particular, to power loss operations for such processing devices.

BACKGROUND

Electronic devices are continually facing performance pressures including providing increased computing power and providing varied control capabilities. The performance pressures also include needing ever increasing abilities to extend battery life or generally improve power efficiency of a computing device's operation. Accordingly, computing devices of various types include varying ways of enter low power modes that allow the given device to use less power. Low power modes generally include stopping use of various features or powering down certain peripherals for the device.

The lowest of the low power modes include actually removing power from a device's central processing unit (“CPU”). Entering into the lowest power modes, however, typically results in such devices not retaining the CPU's state. Therefore, the device must be reset upon wakeup to restore an operating state of the CPU and associated peripherals. A programmer of applications running on such a device is forced to handle this reset condition and manually restore the application's state to where it was before the device entered into deep low power mode, i.e., power down of the CPU. This is especially true as more complex software is used in embedded systems, such software including graphical display applications, radio frequency communications having complex protocol stacks, or real time operating systems. Such applications can require several thousand CPU cycles on device startup to initialize software variables before an intended task begins. In one example, running a C-Init and User-Init processes (initialization processes for the CPU and the user application, respectively) can require up to 101 milliseconds and 298 microseconds, respectively. In addition to the time delay, the rebooting process places a further drain on applicable battery resources as well. This is a painful process for customers using such computing or processing devices subject to interruptible power sources and/or using deep low power modes.

SUMMARY

Generally speaking, pursuant to these various embodiments, a computing device apparatus facilitates use of a low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements such as various state information in non-volatile memory in response to entering the low power mode. A hardware based power management unit is configured to control the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode. Optionally, the device's power management unit is configured to prevent device startup unless enough energy is present on the energy storage unit to complete a round trip restore and save operation.

So configured, the device need not execute a full reset of the CPU during the wake up from a deep low power mode. Instead, the CPU's and associated peripheral's stable operating state parameters are readily available and restorable from the non-volatile storage, which is able to store such information without consuming power. Also, the hardware implementation can be configured to trigger the storage process at a level of applied power sufficient to guarantee availability of enough power (even in a total power loss event) of storage of the CPU's and/or associated peripheral's state. Also, state information known to be corruptible during sudden power down events can be selectively ignored and not stored during the state storage process thereby allowing for only a limited wake up process, which is quicker and less power consuming that a full wake up routine for the CPU. These and other benefits will become apparent through study of the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an example computing device as configured in accordance with various embodiments of the invention;

FIG. 2 is a block diagram of an example computing device with NVL memory disposed adjacent to volatile storage elements as configured in accordance with various embodiments of the invention;

FIG. 3 is a graph illustrating different operating states of a computing device according to available power as configured in accordance with various embodiments of the invention;

FIG. 4 is a graph comparing a prior art approach to start up, low power event, and wake up cycle to a start up, low power event, and wake up cycle of a computing device as configured in accordance with various embodiments of the invention;

FIG. 5 is a block diagram of another example computing device as configured in accordance with various embodiments of the invention;

FIG. 6 is a flow diagram of an example method of operation of a computing device as configured in accordance with various embodiments of the invention.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments. It will further be appreciated that certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. It will also be understood that the terms and expressions used herein have the ordinary technical meaning as is accorded to such terms and expressions by persons skilled in the technical field as set forth above except where different specific meanings have otherwise been set forth herein.

DETAILED DESCRIPTION

Turning now to the figures, especially FIG. 1, an example computing device apparatus 100 that is compatible with many of these teachings will now be described. The computing device 100 includes a central processing unit (“CPU”) 105, a first non-volatile memory 107, a volatile general purpose and state register memory 110, a second non-volatile memory 115, and a number of peripherals or device modules 120. The first non-volatile memory 107 is connected to store software related information such as program and variable data. The memory 110 and configuration registers 125 are volatile storage elements configured to store configuration profile data for currently active settings of the computing device 100 or peripherals 120 associated with the computing device 100. The memory 110 storing data for the CPU 105 may be embedded within the CPU 105, or it may be separate from and associated with the CPU 105. An energy storage unit 130 is connected to provide power to the computing device apparatus 100. Typically, the energy storage unit 130 is a capacitor although other suitable devices can be used. A power management unit 140 is configured to detect multiple levels of available power for the CPU 105 and to effect switching power on or off for the CPU 105. Each of these elements is individually known in the art such that no further description is necessary.

The second non-volatile memory 115 is configured to store hardware (logic) state information. This memory 115 is part of a non-volatile sub-system 150, which includes a non-volatile controller 151 configured to control the non-volatile memory 115 and have direct access to volatile storage elements 110, 125 embedded in or associated with one or more of the central processing unit or one or more peripherals. The NVL memory 115 itself may be a flash-type memory, a ferro-magnetic random access memory (“FRAM”) based state retention technology that combines characteristics of FRAM memory with current data retention methods, or other technologies with similar features such as spin-torque magnetoresistive random access memory (“MRAM”) or resistive access memory (“RRAM”). Such memory technology is known in the art and requires no further description; see, for example, regarding FRAM U.S. Patent Application Publication Number 2014/0075088, which is incorporated herein by reference in its entirety. Typically, the non-volatile memory 115 will have a high write cycle endurance of 10¹⁰ or higher to be able to provide a sufficient shelf life for expected cycling of the device 100 during normal use.

Depending on the particular implementation, the NVL sub-system 150 may include any of a variety of aspects. Such systems typically include an NVL clock 152. Optionally, input and output multiplexers 154 and 156 control connection of individual volatile storage elements 125, 110 to an individual one or rows of one NVL array 115. In such an implementation, a dedicated bus 160 separate from a system bus 165 connects the non-volatile logic array(s) 115 to the configuration registers 125 and memory 110. The dedicated bus 160 allows direct connection to the configuration registers 125 and memory 110 to operate under the control of the NVL subsystem 150. Similarly, another separate bus 167 can be implemented to directly connect the configuration registers 125 and memory 110 to the input multiplexer 154 for connection to the NVL array(s) 115. Therefore, the transfer of data from the volatile storage to the NVL storage can be done under the NVL subsystem's hardware control.

In another approach illustrated in FIG. 2, separate NVL arrays 215, 216, 217 are disposed physically closely to corresponding volatile storage elements such as groups of flip flops. In the illustrated example, flip flop volatile storage elements 225 and 227, 231 and 233, 235 and 237 are arranged in flip flop clouds 210, 220, 230 corresponding to particular peripherals or CPU subsystems. The NVL controller 251 controls the functioning of each of the arrays 215, 216, 217 to store data from and restore data to their respectively associated flip flops.

Turning again to FIG. 1, the power management unit 140 is configured to interrupt a normal processing order of the CPU 105 to effect entry of the CPU 105 into a low power mode. The entry into a low power mode can be triggered in response to detecting a power loss event initiated by the power management unit 140 due to detection of a power loss scenario or proactively initiated by the CPU 105 to save energy. Thus, the power management unit 140 is able to initiate the process in response to either a power loss event or simply an affirmative entry into a low power mode for power savings.

The energy storage unit 130 is configured to hold enough energy to operate the computing device apparatus 100 after removal of normal operating power from the computing device apparatus 100. The power management unit 140 in turn uses the energy stored in the energy storage device 130 to trigger the non-volatile memory controller 151 to store data stored in the volatile storage elements 110, 125 in the non-volatile memory 115 in response to entering into the low power mode. After the data is saved in the non-volatile memory 115, the power management unit 140 effects switching off power to at least the CPU 105 as part of entering the low power mode. Optionally, the power management unit 140 is configured to prevent a startup of the computing device apparatus 100 unless enough energy is present on the energy storage unit 130 to complete a round trip restore and save operation to ensure stability of the device. One advantage of such an approach can be understood with reference to the example implementation illustrated in FIG. 3.

FIG. 3 illustrates an amount of power available to a device over the course of various operation conditions. The device of this example operates with a supply voltage supervisor (SVS), which indicates when the available power is within a particular range. The available power is illustrated with markers V_(SVS-ON), V_(SVM), and V_(SVS-OFF) illustrating cut-off values of the power with respect to operation of the device. Here, V_(SVS-ON), represents a typical normal power level for a device operating normally, for example, 2.5 volts. V_(SVM) represents a minimum power level, for example, 2.2 volts, available such that if outside power is cut, the energy storage unit 130 is holding sufficient power to complete a data storage operation to the NVL memory 115. V_(SVS-OFF) represents the cut-off in minimum power to allow for operations during entry into a low power mode, for example, 1.8 volts. In operation, the power management unit 140 will monitor the available power using known methods such as an analog comparator on the external power supply. Should the available power drop below the V_(SVM) level, the power management unit 140 interrupts operation of the CPU 105 (interrupt service routine, ISR) to begin entry into the low power mode, including saving data from the volatile storage elements 110 and 125 to the NVL memory 115. In a typical implementation, the interrupt and data save operations take only about 100 microseconds, so the amount of energy stored in the energy storage unit 130 need not be large. That said, the size of the energy storage unit 130 can be tailored to a particular device design, whereby a larger energy storage can be used where a more power intensive process for entry into the low power mode is expected.

Referring again to FIG. 1, the low power mode is exited in response to detecting either restoration of power in the event of power loss or a wakeup request when the low power mode was entered as part of a power savings strategy. In response to detecting the restoration of power to the computing device apparatus 100 or the wakeup request from the CPU's 105 power off state, the power management unit 140 triggers the non-volatile memory controller 151 to restore the data to the volatile storage elements 110, 125 from the non-volatile memory 115 prior to execution of a wake up process for the CPU 105 from the low power mode.

Such a wake up process is illustrated in FIG. 3, where after completing an NVL save operation when the available power dropped below the V_(SVS-OFF) level, the power returns to the V_(SVS-ON) level. In this example, this level is the minimum power needed to complete a round trip restore and store operation. As illustrated in FIG. 3, when available power reaches the V_(SVS-ON) ON level, the power management unit 140 triggers restoration of the data from NVL memory 115 to the respective volatile storage elements, and the user application is continuous from the state before the ISR was executed. Assuming power is cut when the restoration process begins, the available power after the restoration and application execution process is about the V_(SVM) level, which triggers another NVL store operation during re-entry into the low power mode. So configured, overall stability of the device is improved because device state data needed for restart is sure to be resaved and not lost due to immediate loss of power upon restarting of the device.

As part of the wakeup process, the CPU 105 and the power management unit are configured to not automatically trigger execution of a cold boot initialization process in response to the detecting the restoration of power or the wake up request. By using the hardware configuration for automatically restoring the data from the NVL memory 115, the computing device can be placed into a state ready for execution of a loaded application faster and more efficiently than by executing the cold boot processing, including, for example, the C-Init and user-Init processes.

Efficiencies gained through application of these concepts are illustrated in the examples of FIG. 4. After an initial boot sequence (C-startup) and initialization sequence for the device and its application(s), the device's application(s) run normally. In the event of a power loss, the energy storage unit provides sufficient power to execute the described NVL save as part of the entry into the corresponding low power mode. When power is again available, instead of re-running the boot sequence and initialization sequence as illustrated in the prior art process, the NVL restore process followed by a “housekeeping” process is performed, which processes are completed in a much shorter amount of time as compared to the prior art power up process. In the example illustrated in FIG. 4, the device's application is able to start when using the NVL approach at a point in time where a prior art device is still completing its boot sequence, resulting in significant time and power savings. A further advantage is illustrated in that because of the relatively short wake up process, the device using the NVL approach is ready for another power loss event sooner than the prior art device. Thus, the described approach reduces the chances that power is lost during a critical portion of the boot sequence, which in turn provides improved overall stability of the device's operation.

With reference again to FIG. 1, the data stored in the NVL memory 115 during the entry into the low power mode represents a state of one or more of the CPU 105 or one or more peripherals 120. For example, the NVL memory controller 151 is configured to effect storing in the NVL memory 115 the state of the CPU 105 by storing one or more of program counters, stack pointers, status registers, general purpose registers, or other key state information of the CPU 105. Similarly, the NVL memory controller 151 is configured to effect storing in the NVL memory 115 the state of the one or more peripherals 120 associated with the CPU 105 by storing one or more of peripheral configuration registers, peripheral state registers, peripheral status registers, peripheral data buffers, and other key peripheral state information that may be stored in active settings configuration registers 125 associated with the peripherals 120. The state's static image could be restored upon each system reset or power up reset so that a stable and repeatable machine state can be recovered.

Certain data stored in the volatile storage 110 and 125 may not be stored in various approaches where such data is known to be unreliable or unhelpful during the restart operation. For example, the non-volatile memory controller may be configured to not store any one or combination of bus interface state information, serial communication module information, state machine information, or pipeline register information for the CPU 105 in response to entering the low power mode. Such information is not needed if the transition to the deep low power mode comes from a first low power mode where various ones of these aspects are already in an idle mode. Such parameters can be reset during the above mentioned “housekeeping” process, which is analogous to a typical wake up from an intermediate low power mode to reset these limited parameters. Because there is a relatively small number of such parameters subject to reset during the limited reboot, the wake up process remains much shorter in duration as illustrated in FIG. 4.

Turning to FIG. 5, one example implementation of the type of system and interactions used for the described processes will be discussed. Here, the CPU 505 interacts with a power management unit 540 in the form of a state machine wrapper controlled at least in part by the NVL controller 551, illustrated here as a hardware implemented state machine. An advanced peripheral bus (APB) connects the CPU 505 and the power management unit and NVL control and status register (CSR) 541. The CPU 505 is further configured to receive a non-maskable interrupt (NMI) request signal from the NVL controller 551 to interrupt the CPU's normal process during entry into a low power mode, such as in response to detection of a power loss event. A reset control module 542 interacts with the NVL controller 551 to provide a system reset signal. A shut down control module 543 receives a trigger signal from the CPU 505 and interacts with the NVL controller 551 to trigger a transition to a low power mode in response to receipt of the CPU's trigger signal. The NVL controller 551 controls the NVL subsystem 555, which includes the NVL arrays 556, to control the automatic saving of information from the volatile storage elements to the NVL arrays 556 during transition to a low power mode and restoring that information back to the volatile storage elements on wake up. An oscillator 570 and clock divider 575 provide the various clock signals for the system. So configured, the hardware based state machine controls the storage and restoring of state machine information to provide improved wake up times from a low power mode.

FIG. 6 illustrates one example method of operation for a device in accord with these teachings. A computing device with a CPU and peripheral devices operates in a normal mode of operation at the Active Application step 605. If the device is newly started, it will reach this Active Application step 605 after the reset condition 610 triggers the boot code 615 to complete a cold boot, C-Init 620 to initialize the device, and a User-Init process 625 to initialize the device's application. In another approach, a watch dog process 630 may trigger the C-Init 620 and following processes.

A device with a normally operating active application 605 uses hardware of the computing device including a power management unit to detect a low power event for the processing device. As illustrated in FIG. 6, the low power event can be initiated by the power management unit due to detection of a power loss scenario via step 635 or initiated by the central processing unit via an active interrupt 640 to save energy. In either case, in response to detecting the low power event, the device uses energy stored in an energy storage device for the computing device to control entry into a first low power mode 645. In this example, after entry into the low power mode 645, the device may transition to a deep low power mode. This transition includes triggering a non-volatile memory controller to store data stored in the volatile storage elements in a non-volatile memory having direct physical access to the volatile storage elements at the NVL save step 650. After the data is saved, power is switched off to at least the CPU at step 655, completing the device's transition to a deep low power mode, i.e., an NVL low power mode or power loss state 660.

During the deep low power mode state 660, the power management unit detects either restoration of power past a brownout level at step 665 to the computing device apparatus or a wakeup request from the central computing unit's power off state. In response to detecting the restoration of power or the wake up request, a low dropout voltage regulator is triggered on 670, and the non-volatile memory controller is triggered to restore 675 the data to the volatile storage elements from the non-volatile memory. With the state data restored, the device is back to a low power mode 680 from which a subsequent wake up process 685 for the central processing unit can be efficiently executed. The wake up process 685 includes a minimal clean-up operation compared to a typical prior cold boot wake up process, wherein the minimal clean-up operation is typically targeted to unstable variables whose storage in a NVL memory would not contribute to stable operation of the device.

So configured, this implementation of non-volatile logic allows the construction of a computing system that may only go through the initialization cycle once in its lifetime, even if the power supply is interrupted. The device state (CPU and peripherals) can be saved while the device is in a low power mode prior to entering a deep low power mode. From a software point of view operating on the device, the next power cycle will look like a simple wakeup from low power mode and not like a device startup, thereby conserving power and time. Additional advantages for executing this process during a low power mode include that because the system is inactive and all clocks are stopped (fixed state), the process may use a known and proven method to go into and come out of low power mode. Also, existing software supports low power mode operation today such that no new concept need be learned to implement. Moreover, the defined state allows for not saving all data from all data storage elements, for instance all flip-flops (area, power, wake up time saving). For example, the bus interface is idle such that there is no need to save idle state, serial communication is stopped such that there is no need to save serializer data, the state machine is idle such that there is no need to save idle state, pipeline registers in the CPU and peripherals are flushed because no save is needed in view of the separate non-volatile storage for storing that information, and a controlled stop/start via low power mode allows for software interaction for clean entry and exit of the deep low power mode NVL save and restore process.

Those skilled in the art will recognize that a wide variety of modifications, alterations, and combinations can be made with respect to the above described embodiments without departing from the scope of the invention, and that such modifications, alterations, and combinations are to be viewed as being within the ambit of the inventive concept. 

What is claimed is:
 1. A system comprising: an input; an output; and a controller coupled to the input and the output, the controller including a non-volatile memory, wherein: in response to a signal on the input corresponding to a first power state, the controller is configured to: transmit an interrupt on the output; and transfer data in a volatile memory to the non-volatile memory; and in response to the signal on the input indicating a second power state, the controller is configured to transfer the data in the non-volatile memory to the volatile memory.
 2. The system of claim 1, wherein: the data includes one of program counters, stack pointers, status registers, and general purpose registers.
 3. The system of claim 1, wherein: the data includes one of peripheral configuration registers, peripheral state registers, peripheral status registers, and peripheral data buffers.
 4. The system of claim 1, wherein: the controller is configured to not transfer portions of the data in the volatile memory that include bus interface state information, serial communication module information, state machine information, or pipeline register information.
 5. The system of claim 1, further comprising: a power control module coupled to the controller and configured to receive the signal on the input.
 6. The system of claim 1, further comprising: a status register coupled to the controller at a first connection; and the status register coupled to a bus at a second connection, the status register configured to store control and status information.
 7. The system of claim 1, further comprising: a reset control module coupled to the controller, wherein the reset control module is configured to provide a system reset signal to the controller.
 8. The system of claim 7, wherein: in response to the system reset signal at the controller; the controller is configured to transfer the data in the non-volatile memory to the volatile memory.
 9. The system of claim 1, wherein: the first power state is a first transition to a low power level; and the second power state is a second transition to a high power level.
 10. The system of claim 1, wherein: the controller is configured to determine the first power state; and in response to the controller determining the first power state, the controller is configured to: transmit the interrupt on the output; and transfer the data in the volatile memory to the non-volatile memory.
 11. A method comprising: determining, by a controller, a first power state; in response to determining the first power state: transmitting, by the controller, an interrupt; and transferring, by the controller, data in a volatile memory to a non-volatile memory; determining, by the controller, a second power state; and in response to determining the second power state, transferring, by the controller the data in the non-volatile memory to the volatile memory.
 12. The method of claim 11, wherein: the data includes one of program counters, stack pointers, status registers, and general purpose registers.
 13. The method of claim 11, wherein: the data includes one of peripheral configuration registers, peripheral state registers, peripheral status registers, and peripheral data buffers.
 14. The method of claim 11, wherein: the transferring, by the controller, of the data in the volatile memory to the non-volatile memory excludes portions of the data in the volatile memory that include bus interface state information, serial communication module information, state machine information, or pipeline register information.
 15. The method of claim 11, further comprising: receiving, by the controller, a shut-down signal from a power control module; and in response to receiving the shut-down signal: transmitting, by the controller, the interrupt; and transferring, by the controller, the data in the volatile memory to the non-volatile memory.
 16. The method of claim 11, further comprising: storing, by a status register, control and status information; wherein the status register is coupled to the controller at a first connection and the status register is coupled to a bus at a second connection.
 17. The method of claim 11, further comprising: detecting, by the controller, a system reset signal from a reset control module coupled to the controller.
 18. The method of claim 17, wherein: in response to the system reset signal at the controller; the controller is configured to transfer the data in the non-volatile memory to the volatile memory.
 19. The method of claim 11, wherein: the first power state is a first transition to a low power level; and the second power state is a second transition to a high power level.
 20. The method of claim 11, wherein: the controller is configured to determine the first power state; and in response to the controller determining the first power state, the controller is configured to: transmit the interrupt; and transfer the data in the volatile memory to the non-volatile memory. 